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DM74LS670 3-STATE 4-by-4 Register File
August 1986 Revised March 2000
DM74LS670 3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits writing into one location, and reading from another word location, simultaneously. Four data inputs are available to supply the word to be stored. Location of the word is determined by the write select inputs A and B, in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high level signal is desired from the output, a high level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are HIGH. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, GW, is HIGH, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, GR, is HIGH, the data outputs are inhibited and go into the high impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. This arrangement--data entry addressing separate from data read addressing and individual sense line -- eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 ns typical) and the read time (24 ns typical). The register file has a non-volatile readout in that data is not lost when addressed. All inputs (except read enable and write enable) are buffered to lower the drive requirements to one normal Series DM74LS load, and input clamping diodes minimize switching transients to simplify system design. High speed, double ended AND-OR-INVERT gates are employed for the read-address function and have high sink current, 3-STATE outputs. Up to 128 of these outputs may be wire-AND connected for increasing the capacity up to 512 words. Any number of these registers may be paralleled to provide nbit word length.
Features
s For use as: Scratch pad memory Buffer storage between processors Bit storage in fast multiplication designs s Separate read/write addressing permits simultaneous reading and writing s Organized as 4 words of 4 bits s Expandable to 512 words of n-bits s 3-STATE versions of DM74LS170 s Fast access times 20 ns typ
Ordering Code:
Order Number DM74LS670M DM74LS670N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS006436
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DM74LS670
Connection Diagram
Function Tables Write Table
Write Inputs WB L L H H X WA L H L H X GW L L L L H 0 Q=D Q0 Q0 Q0 Q0 1 Q0 Q=D Q0 Q0 Q0 (Note 1)(Note 2) Word 2 Q0 Q0 Q=D Q0 Q0 3 Q0 Q0 Q0 Q=D Q0 L L H H X
Read Table
Read Inputs RB RA L H L H X GR L L L L H
(Note 3) Outputs Q1 WOB1 W1B1 W2B1 W3B1 Z Q2 WOB2 W1B2 W2B2 W3B2 Z Q3 WOB3 W1B3 W2B3 W3B3 Z Q4 WOB4 W1B4 W2B4 W3B4 Z
H = HIGH Level
L = LOW Level
X = Don't Care
Z = High Impedance (OFF)
Note 1: (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. Note 2: Q0 = The level of Q before the indicated input conditions were established. Note 3: WOB1 = The first bit of word 0, etc.
Logic Diagram
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DM74LS670
Absolute Maximum Ratings(Note 4)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL tW tSU tH tLATCH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Write Enable Pulse Width (Note 5) Setup Time (Note 5)(Note 6) Hold Time (Note 5)(Note 6) Data WA , W B Data WA , W B 25 10 15 15 5 25 0 70 Parameter Min 4.75 2 0.8 -2.6 24 Nom 5 Max 5.25 Units V V V mA mA ns ns ns ns C
Latch Time for New Data (Note 5)(Note 7) Free Air Operating Temperature
Note 5: TA = 25C and VCC = 5V. Note 6: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the previous address, tSETUP (WA, W B) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tH (WA, WB) will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into. Note 7: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from a location immediately after that location has received new data.
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DM74LS670
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOZH IOZL IOS ICC Off-State Output Current with Off-State Output Current with Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max IOL = Max, VIH = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max, VO = 2.7V VCC = Max, VO = 0.4V VCC = Max (Note 9) VCC = Max (Note 10) -20 30 D, R or W GW GR D, R or W GW GR D, R or W GW GR HIGH Level Output Voltage Applied VIH = Min, VIL = Max LOW Level Output Voltage Applied VIH = Min, VIL = Max 2.4 3.4 0.34 0.5 0.1 0.2 0.3 20 40 60 -0.4 -0.8 -1.2 20 -20 -100 50 A A mA mA mA A mA Min Typ (Note 8) Max -1.5 Units V V V
Note 8: All typicals are at VCC = 5V, TA = 25C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: ICC is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are OPEN.
Switching Characteristics
at VCC = 5V and TA = 25C RL = 667 Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 11) Output Disable Time from LOW Level Output (Note 11)
Note 11: CL = 5 pF.
From (Input) To (Output) Read Select to Q Read Select to Q Write Enable to Q Write Enable to Q Data to Q Data to Q Read Enable to Any Q Read Enable to Any Q Read Enable to Any Q Read Enable to Any Q
CL = 45 pF Min Max 40 45 45 50 45 40 35 40 50 35
CL = 150 pF Min Max 50 55 55 60 55 50 45 50
Units
ns ns ns ns ns ns ns ns ns ns
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DM74LS670
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM74LS670 3-STATE 4-by-4 Register File
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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